1. Field of the Invention
The present invention relates to integrated network devices having Peripheral Component Interconnect (PCI) bridges.
2. Background Art
Peripheral Component Interconnect (PCI) interfaces have been used to provide high-speed connectivity between devices in a multi-device system, such as a processor based system such as a personal computer.
FIG. 1 is a diagram illustrating a conventional implementation of a PCI bus system architecture 100. The system 100 includes a processor 102 coupled to a memory controller 104 via a local bus 106. The processor 102 and the memory controller 104 are coupled to a PCI local bus 106 (labeled PCI Local Bus #0) via a host bridge 108.
The host bridge 108 provides a low latency path through which the processor 102 may directly access PCI devices 110, for example a network interface card 110a providing access to a local area network, a disc drive (SCSI) controller 110b providing access to disk drives 114, an audio card 110c, a motion picture card 110d, or a graphics card 110e configured for driving a monitor 116. The host bridge 108 also provides a high bandwidth path allowing PCI masters on the PCI bus 106 direct access to the system memory 118 via the memory controller 104. A cache memory 120 is independent of the system memory 118 for use by the processor 102.
The term “host bridge” refers to the bridge device 108 that provides access to the system memory 118 for the devices 110 connected to the PCI bus 106. A PCI-to-PCI bridge 122 also may be used to connect a second PCI bus 124 to the PCI bus 106, the second PCI bus 124 configured for connecting other I/O devices 126.
Newer PCI bus protocols are being published, including PCI-X Mode 2, that provide enhanced PCI functionality. These newer PCI bus protocols include the PCI Local Bus Specification, Rev 2.3, the PCI-X Protocol Addendum to the PCI Local Bus Specification, Rev. 2.0a, and the PCI-to-PCI Bridge Architecture Specification, Rev 1.2.
A particular problem encountered during development of new devices that implement the newer PCI bus protocols is the availability of a PCI device having the capabilities of testing the newer PCI bus protocols. For example, development of the host bridge device 108 for use on the PCI bus 106 requires another device 110 or 122 capable of responding to the newer commands specified by the newer PCI bus protocols. Absent the availability of any other device 110 or 122 that implements the newer standard, one may desire to use a duplicate device 108 as a second PCI device (110 or 122) on the PCI bus 108, where the device under test 108 is used as the host bridge and the duplicate device is used as a PCI/PCI-X device 110 or 112.
However, according to the above-described PCI bus specifications, the PCI bus 106 is designed to have a single host device 108 on the PCI bus 106, and all the remaining devices 110 and 122 on the PCI bus 106 are expected to be subservient to the host device 108.
Hence, adding a second bridge device 108 for use as a PCI/PCI-X device 122 for testing and evaluation introduces several conflict issues between the duplicate devices 108 and 122. For example, each bridge device (e.g., 108 and 122) may assume it is the central resource responsible for generating clock signals, reset signals, and initialization patterns on the PCI bus 106. Further, each host bridge (e.g., 108 and 122) may assume that it is the PCI/PCI-X arbiter, creating arbitration conflicts. Finally, address mapping conflicts may occur if both PCI/PCI-X host bridges 108 and 122 are coupled to the same memory system 104 and 118.